UMC and AP Memory announced an AI power delivery collaboration on October 22, 2026, after AP Memory’s S-SiCap Gen2D discrete silicon capacitor designs completed tape-out and initial functional validation in the third quarter. The companies will next move to comprehensive system-level performance and reliability testing of capacitors in substrate packages.
Key Takeaways
- The partnership combines UMC’s deep trench capacitor manufacturing technology with AP Memory’s capacitor designs and system integration.
- Tape-out and initial functional validation are complete; comprehensive system-level testing remains the next step.
- The companies are also exploring capacitor-embedded interposers and landside capacitors.
Table of Contents
- AI power delivery moves closer to the computing die
- Initial validation precedes broader testing
- UMC outlines a wider power-component roadmap
- Conclusion
AI power delivery moves closer to the computing die
The collaboration targets power-efficiency challenges in artificial intelligence and high-performance computing systems. UMC is contributing its deep trench capacitor foundry technology and scalable wafer manufacturing, while AP Memory brings silicon capacitor design and system-level integration.
The companies describe a shift from locating power-stabilization components on circuit boards toward embedding capacitors in interposers or substrates. According to the announcement, placing these components closer to the computing die shortens the power delivery path, improves power integrity and supports more efficient voltage regulation within advanced packages.
The placement depends on the system design: deep trench capacitors can be integrated into an interposer, substrate or the landside of an advanced package.
Initial validation precedes broader testing
The third-quarter milestone covers tape-out and initial functional validation of AP Memory’s S-SiCap Gen2D discrete capacitor designs. It does not mark completion of the comprehensive system-level performance and reliability testing identified as the next development stage.
That testing will evaluate capacitors in substrate packages, targeting support for a range of capacitance and operating-voltage requirements. AP Memory President Ivan Hong said the initial work demonstrated the flexibility and manufacturability of the company’s customized capacitor designs using UMC’s technology.
Beyond the discrete designs, the partners are exploring whether to extend their work to capacitor-embedded interposers and landside capacitors for different system architectures.
UMC outlines a wider power-component roadmap
UMC’s broader roadmap includes discrete and embedded silicon capacitors as well as active components such as internal voltage regulators. The foundry said it is using its advanced packaging capabilities to support denser integration of power components for next-generation data centers.
UMC also said it is investing further in manufacturing capacity for power delivery and heterogeneous integration solutions. The announcement did not specify the size of that investment or a commercial production schedule for the jointly developed capacitors.
Conclusion
The collaboration has cleared an initial design and validation milestone. Its next stage is broader performance and reliability testing, while potential extensions into other capacitor formats remain exploratory.
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